资源列表
EXP4_sec
- 秒表 4个7数码管中的任何一个显示任意按键按下的次数。初始值为0，当计数到9时，下一次数值为0。利用Verilog HDL语言，编程实现上述功能。-Stopwatch
multi
- VHDL Multiplier RTL code-VHDL Multiplier RTL code
DDSsheji
- 再发一个修改的完善的基于FPGA的DDS信号源实现方案-Recurrence of an amendment to improve the FPGA-based realization of the DDS signal source program
max5236
- a program for AD-Wandler max5236 in VHDL Language
ad7304
- a program for AD-Wandler ad7304 in VHDL-Language
xapp462_vhdl
- a example -Code for DCM in language VHDL-a example-Code for DCM in language VHDL
lpm_ram
- 一个基于quartus的LPM_RAM例子，VHDL语言写的，通过仿真测试-Quartus the LPM_RAM based on examples, VHDL language, and through simulation testing
CNT
- 分频的VHDL语言描述，巨简单实用，一看就会，从2到16分频都有，好东西啊。-Sub-band descr iption of the VHDL language, giant simple and practical, one can see, from 2-16 pm band has, ah good things.
Half
- 半整数分频，可以分出x.5的频率，大家请自行研究其他频率。-Half-integer frequency, the frequency may be distinguished x.5, we requested to look into other frequencies.
shift_reg_ps
- this VHDL program can get a 64bit paralel data and make a serial data with SCLK and WCLK.
shift_reg_sp
- this VHDL Progran get a SCLK(seril CLock) and a WCLK(Word CLOCK) with a serial data line and return a 64nits Parallel data.
WRCTRL
- this VHDL Program get a 64 bit data and send it to a SDRAM-controller block to write into SDRAM and then get a 64bits data from SDR-block