资源列表
Avt3S400A_Eval_MB_AN1013_v10_1_03
- This reference design outlines the steps to create a design compatible with a small embedded RTOS, in this case, μC/OS-II from Micrium. This document assumes you have already downloaded Application Note 1013 (AN-1013)
Full_Adder
- Full Adder for Xilinx
traffic
- Light traffic by xilinx
BCD_sevenseg
- BCD seven segment by xilinx
TLC5510
- VHDL实现对TLC5510的控制，带有signaltap仿真图-VHDL implementation of the TLC5510 control, with signaltap simulation diagram
flipflop
- FlipFlop VDHL by xilinx
latch
- Latch VDHL by xilinx
counter
- Ring Counter implemented in VHDL usign finite state machine design.
ADC124
- 采用verilog编写的高速串型AD采集芯片adc124驱动代码，占用le较少，效率高，目前我应用在较多产品上-Verilog prepared using high-speed string-type AD Acquisition chip adc124 driver code, occupation le small, high efficiency, the current I applied to more products
ds18b20s4
- 四路DS18B20的verilog HDL 代码，精度为1℃无须转换数据，根据输入地址改变直接输出结果。占用600个LE资源，相对于单路程序，更为精减-Four DS18B20 the verilog HDL code, and an accuracy of 1 ℃ without converting the data, enter the address change in accordance with the direct output. Occupy 600 LE resources,