资源列表
ondometer
- 用verilog语言编写的运行与FPGA上的基本的频率计程序，有各种数量级的精度，开发环境为quartus2-ondometer written by verilog
processor
- processor design istruction load pipeline ,hazard
I2C_ise9migration
- IIC 的Verilog实现，工程是在Xilinx的ISE9.1上实现的-IIC of the Verilog implementation project was implemented on Xilinx' s ISE9.1
QuadE-ResponderBasedOnVHDL
- 基于VHDL语言开发的四路电子抢答器，开发环境为MAX-Plus2-VHDL language development based on four electronic answering device
TLC5620
- Verilog HDL语言，FPGA实现TLC5620的DAC源代码-Verilog HDL language, FPGA implementation of the DAC TLC5620 source code
DE2_70_TOP
- 在quartus上实现电子锁的设计，采用cyclone的板子，方便设置初始密码，更新密码-Quartus to achieve in the design of electronic locks, using cyclone of the board, easy to set the initial password, update password
divider
- 带时钟及控制的多位除法器设计，利用状态机来实现控制-multi-cycle divider design
DigitalclockinVHDL
- it is the program for VHDL digital clock
HMM
- 有关HMM的MATLAB代码 都在压缩文件了-CODE FOR HMM DOWNLOAD WHEN YOU NEED
clk_divide5
- 五分频电路verilog源码，包含测试文件-Five-frequency circuit verilog source code, including test file
softdrink
- 自动售货机verilog源码,含找零功能，通过Modlesim,leonardo仿真，综合-Vending machine verilog source
verilog_example
- 九个verilog源码例子，包括寄存器，状态机等，含testbench-9 verilog source code examples, including registers, state machines, with testbench