资源列表
sdram
- 用verilog语言编程实现的SDRAM模块，可用于配置在FPGA中-Verilog language programming with the SDRAM module, can be used to configure the FPGA,
DATA
- ８位输出端口模块，可用于配置在FPGA中，verilog语言编程实现-8-bit output port modules can be used to configure the FPGA in, verilog language programming
ALU
- 算术逻辑部件的verilog代码，它能够实现半加器、全加器、比较、按位与、按位或、按位异或、加一、减一的操作-Arithmetic logic unit of the verilog code, it can achieve half adder, full adder, compare, bitwise and, bitwise or, bitwise xor, plus one, minus one operation
FPGACPLD_MSKmod_demod
- FPGACPLD的MSK调制解调的工程应用,要下的赶快-FPGACPLD the MSK modulation and demodulation of engineering applications, it is necessary to quickly Ha ha ha
vhdl_pgms
- Program for Counter, mealy machine, moore machine, ones counter, seven segment with zero blanking and shift register in VHDL.
kj
- FPGA环境下学习用verilog hdc编程，可快速入门 的ppt-FPGA environment for learning programming with verilog hdc, fast entry of ppt
zyg
- 用VHDL控制液晶显示。下面就发一个去年参加CPLD竞赛时编写的一个显示模块。当然，不具通用性，但其中的总控制台方法是原创的，我认为很好用。有空我会梳理出一个通用的流程图，以便广大网友交流学习。
Priority_Encoder
- Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, an Encoder takes all the data inputs one at a time and converts them to a single encoded output. Then, it is a multi-input da
Encoder_Using_Assign_Statement
- Encoder Using Assign Statements: Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, an Encoder takes all the data inputs one at a time and converts them to a single encoded o
electroniccodelockvhdl
- vhdl的电子密码锁This is based on the electronic code lock vhdl curriculum design code- the electronic code lock vhdl curriculum design code
cpu_design
- 包括很多种设计方案，其中复杂cpu满足乘除运算，同时设计中包含设计报告模板。-Including many kinds of designs, which cpu to meet the complex multiplication and division operation at the same time the design includes the design report templates.
vhdl_pgms2
- certain vhdl programs like addition, division, difference etc that can help beginers