资源列表
FPGA_jinyan
- 上面包含了一些基本的FPGA的学习经验，和一些基于NIOS II的几个程序，在本人板子上面验证通过了的。-Above, the FPGA contains some basic learning experience, and a number of several procedures based on NIOS II, above board in my verification has been passed.
multi8x8
- 用VHDL设计应用移位相加原理的8位乘法器，使用QuartusII仿真验证。-VHDL design applications with the principle of adding 8-bit shift multiplier, using QuartusII simulation.
JYSZCCLBQ
- 简易数字滤波器的设计 基于EDA语言 开发平台较广-Simple digital filter design language development platform based on the broader EDA
25
- 电子钟（模式转换24/12进制，校时，校分）-Clock (24/12 hex mode conversion, school hours, school hours)
dsp-book
- 数字信号处理设计参考白皮书，是期望充分发掘Xilinx DSP Slice的DSP设计人员的绝佳参考资料-Digital signal processing design reference White Paper, is expected to fully exploit the DSP Xilinx DSP Slice an excellent reference for designers
sfifo
- 牛逼的娴熟的异步fifo，vhdl程序，波形完美-fifo
paobiao
- verilog代码，跑表计数器程序， 希望能帮到感兴趣的人~-verilog code run led
fpga1
- trés trés interessant-trés trés trés interessant
1024FFVHDL
- 1024点基2时分FFT快速傅立叶变换(vhdl) -1024-point radix-2 FFT Fast Fourier transform peak (vhdl)
IFFT
- 这是关于傅里叶反变换的一个完整的ISE的工程..使用verilog语言-This is on the Fourier transform of a complete anti-ISE project using the verilog language ..
clock_generator
- 基于FPGA的时间转换器的一个ISE工程，使用verilog语音-Converter based on FPGA time a ISE project, use the verilog voice
FIFO
- FPGA实现FIFO模块，用于异步数据处理，作为高速缓冲CACHE-FPGA realization of FIFO module for asynchronous data processing, as the cache CACHE