资源列表
weitb
- 在数字通信中，通常直接从接收到的数字信号中提取位同步信号，这种直接法按其提取同步信号的方式，大致可分为滤波法和锁相法。锁相法是指利用锁相环来提取位同步信号的方法，本设计方案就是基于锁相环的位同步提取方法，能够比较快速地提取位同步时钟，并且设计简单，方便修改参数。采用Quartus II设计软件对系统进行了仿真试验，并用Altera的Cyclone II系列FPGA芯片Ep2c5予以实现。-In digital communication, usually from receiving direc
16weiyunsuanqi
- 16位运算器的设计和实现，具有参考价值，适合vhdl课设-16-bit computing design and the realization of a reference value for class-based vhdl
SOS
- 基于verilog的sos求救信号的编写，适用于quartus ii的开发环境！-Verilog based distress signal written in sos, apply quartus ii development environment!
Frequency-counter
- 基于FPGA的频率计设计。通过FPGA运用、 HDL编程，利用FPGA(现场可编程门阵列)芯片设计了一个8位数字式等精度频率计，该频率计的测量范围为0-100MHZ，利用QUARTUS II集成开发环境进行编辑、综合、波形仿真，并下载到CPLD器件中，经实际电路测试，仿真和实验结果表明，该频率计有较高的实用性和可靠性。-Frequency counter FPGA-based design. By using FPGA, VHDL programming, the use of FPGA (fi
Digital_Clock
- FPGA数字时钟完美通过测试。目标板是ZRTECH的EP2C5T144C8 CORE2-5U核心板及PERI1-8KD配套子卡。-The FPGA digital clock perfect pass the test. The target board is ZRTECH EP2C5T144C8 CORE2-5U core board and PERI1-8KD supporting daughter card.
Verilog
- 东南大学Verilog HDL经典讲义，有助于初学者的学习-Southeast University, Verilog HDL classic lectures to help beginners learn
adc
- 用verilog实现TLC549——AD采集实验，采集完的数送给数码管显示-TLC549- AD Acquisition experimental collection finished with verilog number sent to the digital tube display
shuzizhong
- 数字钟，通过FPGA实现了各种功能，课程设计所做，因为代码简单，没有分模块，一个程序写完了。-Responder, through the FPGA to achieve a variety of functions, curriculum design done, because the code is simple, there is no sub-module, a program finished.
GraphicEqualizer
- Graphic Equalizer sample display -Graphic Equalizer sample display
USB2UART
- usb串口通信的固件程序与FPGA控制程序-usb serial communication firmware and FPGA control program
fft
- 快速傅立叶变换（FFT）的FPGA实现,本系统采用了不同点数基2的复FFT。-Fast Fourier Transform (FFT) of the FPGA, the system uses two different points-based complex FFT.
xiyiji
- 基于开发板制成的洗衣机，对于大学生的课程设计很适用-Washer made based development board, designed for college courses is applicable