资源列表
fpgadsp.rar
- system gen & accel dsp 培训资料,system gen & accel dsp
shifter.rar
- verilog实现的“并行输入、并行输出移位寄存器”,verilog to achieve a " parallel input, parallel output shift register"
FPGACPLD_protel1.rar
- protel fpga常用封装库1，非常难找的,protel fpga library a popular package is very difficult to find the
ddr_sdram_controller_vhdl.rar
- DDR SDRAM控制器的VHDL代码已经测试,DDR SDRAM controller VHDL code
HY57V641620HG.vp.rar
- Hynix公司8M Byte SDR SDRAM的Verilog语言仿真实现,Hynix' s 8M Byte SDR SDRAM Simulation of the Verilog language
DDSsinROMsample.rar
- fpga DDS ROM数据正弦波形正半周采样程序,fpga DDS ROM sinusoidal waveform is a half weeks of data sampling procedures
DE2_70_D5M_LTM_NIOS_capture.zi
- 本文提供一個CMOS Controller，讓Nios II可以藉由CMOS Controller控制CMOS，並能讀出CMOS放在SDRAM中的影像。运行在DE2-70平台上,This article provides a CMOS Controller, so that Nios II can take advantage of CMOS Controller control CMOS, and allowed to deliver on the SDRAM in the CMOS imag
shuma.rar
- 数码管动态显示程序，verilog的，已经调试成功,verilog
DE2_70_LTM_CCD.zip
- A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM. ,A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.
cs555.rar
- 这是一个用VHDL语言写的用状态机控制cs5550进行AD转换的代码，里边包含用逻辑分析仪进行分析的文件。具有很强的可移植性。,This is a work written in VHDL language using state machine control cs5550 for AD conversion code inside that contains the logic analyzer with an analysis of documents. Are highly portab
filter_verilog.rar
- 用verilog实现的低通滤波器，输入输出精度为64位，并附有测试程序。,Use verilog to achieve a low-pass filter, input and output accuracy of 64, together with testing procedures.
adder.rar
- 一位全加器可由两个一位半加器与一个或门构成，该设计利用层次结构描述法，首先设计半加器电路，将其打包为半加器模块；然后在顶层调用半加器模块组成全加器电路,A full adder can be two a half-adder and an OR gate structure, the design is the use of hierarchical descr iption method, first of all the design half-adder circuit, be packa