资源列表
firshuzilvboqi
- :介绍了基于FPGA的FIR数字滤波器的设计与实现,该设计利用Matlab工具箱设计窗函数计算FIR滤波器系数,并通过VHDL层次化设计方法,同时FPGA与单片机有机结合,采用C51及VHDL语言模块化的设计思想及进行优化编程,有效实现了键盘可设置参数及LCD显示。结果表明此实现结构能进一步完善数据的快速处理和有效控制,提高了设计的灵活性、可靠性和功能的可扩展性。 -: This paper presents FPGA-based FIR digital filter design and
clock_divider
- 任意小数分频器产生原理，及详细说明文档，任意数分频(包括奇偶数和小数)的设计方法(含VHDL例子)-Generate arbitrary decimal divider principle, and detailed descr iption of the document, arbitrary number of sub-frequency (including the odd-even numbers and decimals) design methods (including VHDL
CPLDQQ2812
- QQ2812开发板的CPLD源代码，CPLD芯片为ALTERA公司MAX3000A系列芯片-QQ2812 development board
VHDL1
- 数字电子时钟中，秒和分要求要有60进制计数器和24进制计数器，此为60进制计数器-Digital electronic clock, the seconds and sub-band requires 60 counters and 24-ary counter, this counter is 60 hexadecimal
TEST7
- 这是一个键盘扫描的程序 没有去抖电路 但是还是很好用的 我测试过 很好用的-This is a keyboard scanning procedure did not go to shake or a good circuit but I tested used a very good use
vhdl_case
- 这是一个两个状态机的文件 都是很输入有关的 是我很我的同学的 希望对大家还是有点帮助的 -This is a two state machine documents are related to the importation of my classmates I hope all of you a little help
seqdet
- 用verilog鉴定10010序列，用verilog鉴定10010序列-10010 sequence identification using Verilog with Verilog identification sequence 10010
TEST5
- 这个是秒表的程序,很简单,不要取笑,多多交流了-This is a stopwatch procedures, is very simple, do not make fun of, a lot of exchange of
3
- 频率计设计 由多个部分组成 主要为了学习VHDL的同学提供 加油 加油 加油 加油 加油 加油 加油 -Cymometer designed by a number of major parts of the students to learn VHDL to provide refueling tanker refueling tanker refueling tanker refueling
vhdlforlab
- vhdl语言程序的a244器件的程序 希望对大家的学习有所帮助-VHDL language procedures a244 device procedures for all of us want to be helpful to learn
lab_6_1
- 用VHDL描述的74ls163,模拟实现其时序逻辑功能-Using VHDL described 74ls163, simulation to achieve its sequential logic functions
i2c
- I2C程序， 已经验证过了 ，大家看看看！-I2C procedures, has already been verified, we take a look at to see!