资源列表
serial_usb
- fpga实现usb口测试 fpga/altera-usb port test fpga/altera
vga
- fpga 实现vga fpga/altera-fpga implementation vga fpga/altera
veri_adder
- verilog VHDL codes for adders
pwm_gen
- PWM _Generator VHDL code
pid_vhdl_code
- PID controller... ... ... ... ... ... ... ... ..... -PID controller.....................................................
pushbutton_wrapper
- 赛灵思FPAG开发板上的按钮VHDL源代码，对于硬件设计可以借鉴的好材料！-Xilinx development board FPAG button VHDL source code for the hardware design can learn from the good material!
dip_switch_wrapper
- 赛灵思开发板dip开关的VHDL源代码，对于硬件开发参考的材料！-Xilinx development board dip switches, VHDL source code for the hardware development of reference materials!
clock_generator_0_wrapper
- 赛灵思FPGA开发板上时钟源的VHDL源代码，可作为硬件设计参考资料！-Xilinx FPGA development board clock source of the VHDL source code, hardware design can be used as reference!
debug_module_wrapper
- 赛灵思FPGA开发板上调试模块的VHDL源代码，可作为硬件设计参考资料！-Xilinx FPGA development board debug module' s VHDL source code, hardware design can be used as reference!
bram_block_0_wrapper
- 赛灵思FPGA开发板上BRAM模块VHDL源代码，可作为硬件设计参考资料！-Xilinx FPGA development board BRAM module VHDL source code, hardware design can be used as reference!
modelsim
- 用verilog编写的基于流水线结构的16阶滤波器的实现 -filter
Mars-EP1C6-F_code1
- 此包中为FPGA学习板中的基础实验代码.共包括8个实验源代码:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机和四位比较器.-In this package for the FPGA board to study the basis of the experiment code. A total of eight experiments, including source code: 8-bit priority encoder, multipliers, mul