资源列表
vhdl
- 用到了硬件的读写进程,多端口的地址分配,有限资源的计数器编写-Use of the hardware to read and write process, the multi-port addresses allocation of limited resources to prepare counter
clock
- 一个可调时间的时钟，包括分频器，时分秒显示，数码管驱动-An adjustable time clock, including the divider, when minutes and seconds display, the digital control-driven
CummingsHDLCON1999_BehavioralDelays_Rev1_1
- Verilog models with behavioral delays
Metastability_in_FPGA
- Don t Let Metastability Cause Problems in Your FPGA-Based Design
counter
- 用VHDL语言实现的计时器，最大计时为24小时，计时精度为1ms，设有复位和暂停功能，使用的晶振频率为50Hz。-VHDL language implementation of the timer with a maximum time of 24 hours, timing accuracy of 1ms, with reset, and pause functions, using the crystal oscillator frequency is 50Hz.
test4adder
- 用VHDL实现的加法器，可以进行减法运算，运算结果通过数码管显示，由于设计时的按键较少，所以运算的范围比较小，只能计算64以内的加减法运算，可以作为学习资料来参考。-Adder using VHDL implementation can be carried out subtraction, calculation resulted in the adoption of digital tube display, due to the design of the keys relatively
manchester_encoding
- 用电压的变化表示0和1.规定在每个码元中间发生跳变.高→ 低的跳变表示0,低→ 高的跳变表示为1,也就是用01表示0,用10表示1.每个码元中间都要发生跳变,接收端可将此变化提取出来作为同步信号,使接收端的时钟与发送设备的时钟保持一致.-With the voltage changes that have 0 and 1. Provides that each code element transitions occurring in the middle. High to low transi
8-bit_Alu
- This is a simple 8bit ALU that is coded in VHDL
100vhdl_project
- 熟悉VHDL语言的小程序和.pdf文档，例如：乘法器、比较器和交通等设计等100个小例子，非常适合初学者。-Familiar with the VHDL language, applets and. Pdf documents, such as: multiplier, comparator and transportation design 100 small example, very suitable for beginners.
rd_utilities
- verilog utilities such as buffers, invertersm and gates, etc
RD_util2
- verilog utilities such as and, xor, xnor etc
DisplayLCD
- 显示1602,将整数转化为BCD码 开发环境是Quartus II7.2-LCD1602 display develop software is Quartus II7.2