资源列表
boxingfashengqi
- 能产生方波和三角波的信号发生器，以时钟信号为基准，输出时可以选择一种信号输出。-Can produce a square wave and triangular wave signal generator to the reference clock signal, a signal output can be selected output.
DDS
- DDS正弦信号发生器，编译通过，在线调试成功。-DDS sine wave signal generator, compiler 100 , debugging success online.
traffic_C4_6
- this a traffic light controller programme. the code is wirted by verilog hdl. -this is a traffic light controller programme. the code is wirted by verilog hdl.
correlation_despreading
- VHDL code for synchronization before despreading
mulacc
- vhdl code for multiplication and accumulation
multiply_stdlogicvector
- vhdl code for multiplying two std_logic_vector
shitreg
- vhdl code for implementation of shift register
balle3D
- Altera_DE2-70应用乒乓球游戏.-Altera_DE2-70 Application table tennis game.
elevator
- fpga电梯控制程序，有很强的参考价值，希望大家能够喜欢。-fpga elevator control procedures, there is a strong reference value, I hope you will enjoy it.
rdf0125_fft_sim_tutorial
- FPGA硬件协仿真，采用jtag的仿真例子，如果自己设计的板卡，需要加上BSP文件，bsp的文件格式在fpga的安装目录-ISim Hardware Co-Simulation Tutorial: Accelerating Floating Point Fast Fourier Transform Simulation
EDK_IP_ISE
- 最近忙一个EDK的小工程，自己定义个用Create or Import Peripheral 定义了IP，在里面要用到ISE的IP.困扰了一段时间！经过群里、论坛上一些朋友的帮助 终于OK了-EDK little busy recently a project with their own definition of a Create or Import Peripheral define the IP, in which to use the ISE IP. Troubled for some
Zed_vga_hdmi_720p
- 开发板zedboard上的hdmi的显示，采用开发工具ise，熟悉ideo的时序，推荐给大家-Hdmi display board zedboard on using development tools ise, familiar ideo timing and recommend it to everyone