资源列表
fp-im-of
- its abt in vhdl ,frequency estiator
testMem
- Example of a FPGA memory controler
cy7c1371c_vhdl_10.zip
- cy7c1371c ZBT SRAM 的仿真模型，VHDL编写。,the simulate model of cy7c1371c,VHDL language.
Digital_Clock_VHDL_s0g0
- Digital Clock in Assembly 我的一个大学满分VHDL作品，数字石英钟的模拟程序。-Digital Clock in the Assembly a perfect score University VHDL works , the number of quartz crystal clock the simulation program.
VHDLqiangdaqi
- VHDL四路抢答器该任务分成七个模块进行设计，分别为：抢答器鉴别模块、抢答器计时模块、抢答器记分模块、分频模块、译码模块、数选模块、报警模块，最后是撰写顶层文件。-VHDL four Responder divided into seven modules of the design task, namely: Responder identification module, timing module Responder, Responder scoring module, frequency
DSP_FIR_Lab
- DSP的FIR实验，包含三种FIR实现形式，直接型，转置型，累加型，并且附带testbench,经过modesim测试没问题。-This is DSP FIR lab, it includes there forms to implement FIR, direct form, transposed form and time mulitple form, all code has been tested on Modesim.
daima
- 2选一功能选择器！加法器，8选一等，一个个简单却很常用的单个模块！-2 Select a function selector! Adder, 8-to-first-class, a simple single module is very popular!
psshubiaojiekou
- 这是比较有倾向的程序，是属于ps/2 鼠标连接接口程序，希望有用的人可以得到应用-This tendency procedures are ps/2 mouse connector interface program, I hope useful can be applied
stopwatch
- 具有暂停、清零功能的秒表,采用结构化方法设计-Stopwatch with the function of pause and clearing.
frenq
- 用于等精度频率计测量程序,可下载至FPGA,或CPLD芯片中-Used for other precision frequency measurement procedures
cpu
- vhdl代码实现8位cpu功能，包含自编写指令序列
ddr3
- VHDL code sample.this files is the VHDL code for using of DDR3 and DDR2 SDRAM.