资源列表
VisualizingTimeandFrequencyDomain
- Visualizing Time and Frequency Domain
yixiang
- 数字式移相信号发生器可以产生预置频率的正弦信号，也可产生预置相位差的两路同频正弦信号，并能显示预置频率或相位差值；-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that
MuxDemux_E1_E3
- E3 -Mux / Demux - Multiplexer of 16 E1 Channels-E3 -Mux / Demux - Multiplexer of 16 E1 Channels
miaobiao
- 秒表的VHDL语言程序，是实验课上一个课程设计，非常正确，非常好用。-Stopwatch VHDL language program is the experimental class curriculum design, very correct, very easy to use.
2009832321345283
- 两位十进制数字锁 实现数字锁功能 能够有灯亮在正确时 也有灯灭 在错误时-Two decimal number lock function of the digital lock on the right to have lights off when there is light at the wrong time
cell
- codes for DP ram synthesizable
Solutions
- `timescale 1ns / 1ps module AND_OR(INP, OUT1) input [3:0] INP output OUT1 wire SIG1, SIG2 MY_AND2 U0 (.A(INP[0]), .B(INP[1]), .C(SIG1)) MY_AND2 U1 (.A(INP[2]), .B(INP[3]), .C(SIG2)) MY_OR2 U2 (.A(SIG1), .B(SIG2), .
uart_0910
- uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of fr
uart transmission rtl level
- UART transmission rtl level
MIPSSYN
- MIPS vhdl code. 8 files in
brom_16x8
- 使用Verilog语言编写的ROM读写程序,使用IP核,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-ROM using Verilog language literacy program, the use of IP core in Xilinx Spartan-6 run through, is a very good program Verlog
des
- VHDL实现的DES密码算法的完整的加解密。-DES