资源列表
2dDCT
- 二维dct算法的fpga实现及验证,采用VHDL语言编写。-2D-dct The FPGA realizing algorithm
sdramtest
- vhdl语言编写读写三星SDRAM程序，包含读写控制程序，地址转化程序，测试模块程序-vhdl language, reading and writing the Samsung SDRAM program, contains the read and write control procedures address conversion program, the test module program
std_logic_arith
- 描述了VHDL加减乘除的最基本的操作，包括重载，最底层的实现，是理解一门语言的最好的途径-VHDL descr iption of the basic operations of addition, subtraction, including overloading, the underlying implementation is the best way to understand a language
crc16
- 一个实现CRC16的VHDL代码，以及说明CRC计算的原理和方法。(a VHDL code for CRC16.)
CSA464
- Verilog - Combinational part of Carry-Save adder, 4 operands 64-bits
0263
- Thermonuclear using weighting factors Can realize the two-dimensional data clustering, For lack of EMD.
fir
- 电源滤波器是由电容、电感和电阻组成的滤波电路。滤波器可以对电源线中特定频率的频点或该频点以外的频率进行有效滤除，得到一个特定频率的电源信号，或消除一个特定频率后的电源信号。(Power filter is composed of capacitance and inductance and resistance of filter circuit.Specific frequency of the filter to the power cord or the point that the
sequential detector
- verilog 固定序列检测器，能够检测10111序列，波形无误。适合Verilog初学者学习(Verilog fixed sequence detector)
CANNY
- 对特定图片进行canny边缘检测。首先是高斯模糊，然后sobel算子处理，再局部极大值确定，最后阈值判断。(Canny edge detection for a particular picture. The first is the Gauss fuzzy, and then the Sobel operator is processed, and then the local maximum is determined, and finally the threshold is judged
lab5
- Verilog lab5 is used for learning vivado
program
- Built in self test to such that it generates non redundant inputs to tester using the concept of galois based primitive polynomial.
nbwpm
- Data packet transfer source program, Chaos indicator for Lyapunov index calculation, Really is a good program.