资源列表
regfile
- 寄存器组，有4个16位寄存器组成，功能可以先读后写再读。-Register set, there are four 16-bit registers, functions can be read before write read.
chufa
- 开放式实验，CPU实验除法器，一个简单的除法器-Open experiment, CPU test divider, a simple divider
cheng
- 开放式实验，CPU的设计，乘法器实验，简单乘法器-Open experiment, CPU design, the multiplier experiment, a simple multiplier
bmd_design
- 基于XILINX VC6LX550T FPGA开发的xapp1052即DMA传输验证程序，接口部分的管脚绑定可根据自身芯片型号进行修改-Verify that the DMA transfer process, pin binding interface part can be modified based on XILINX VC6LX550T FPGA development according to its own chip models xapp1052
Creating-Project-and-IP-Core-in-ISE
- 本文介绍了在ISE环境中如何新建工程，并且定义设置IP核进行开发-This article describes how new construction ISE environment, and define the settings IP core development
fpga_49
- pci接口 spi接口 和 uart接口数据传输 sopc挂载 verilog语言编写-pci interface spi and uart interface data transfer interfaces sopc mount verilog language
pci_test_altera
- pci接口测试，请用quartus12.0打开，否则注释乱码，代码没问题-pci interface testing, please use quartus12.0 open, otherwise garbled notes, code no problem
MCS51_cpld
- VHDL语言编写的cpld与51单片机总线通信程序。结果应用证明。-VHDL language of the CPLD and 51 microcontroller bus communication program. Application results prove.
elevator_fpga
- 基于VHDL的FPGA设计，设计一个4层楼的电梯控制系统。-VHDL-based FPGA design, design elevator control system of a four-storey building.
vga_fpga
- 基于VHDL的FPGA设计，VGA显示设计。-VHDL for FPGA-based design, VGA display design.
clock_fpga
- 基于VHDL的FPGA设计，设计一款多功能的电子定时器，包括计时跟倒计时。-VHDL-based FPGA design, design a versatile electronic timers, including the timing with the countdown.
cordic_fpga
- 基于VHDL的FPGA设计，利用CORDIC IP核设计角度的正余弦算法。-Cosine algorithm VHDL based FPGA designs using CORDIC IP core design angles.