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文件名称:bmd_design

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-12-23
  • 文件大小：
    602.76kb
  • 已下载：
    0次
  • 提 供 者：
    a***
  • 相关连接：
    无
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基于XILINX VC6LX550T FPGA开发的xapp1052即DMA传输验证程序，接口部分的管脚绑定可根据自身芯片型号进行修改-Verify that the DMA transfer process, pin binding interface part can be modified based on XILINX VC6LX550T FPGA development according to its own chip models xapp1052
(系统自动生成,下载前可以参看下载内容)

下载文件列表

bmd_design/bmd_design.gise
bmd_design/bmd_design.xise
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/BMD_128_RX_ENGINE.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/BMD_128_TX_ENGINE.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/BMD_32_RX_ENGINE.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/BMD_32_TX_ENGINE.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/BMD_64_RX_ENGINE.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/BMD_64_TX_ENGINE.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/common/BMD.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/common/BMD_CFG_CTRL.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/common/BMD_EP.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/common/BMD_EP_MEM.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/common/BMD_EP_MEM_ACCESS.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/common/BMD_GEN2.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/common/BMD_INTR_CTRL.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/common/BMD_INTR_CTRL_DELAY.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/common/BMD_PCIE_20.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/common/BMD_RD_THROTTLE.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/common/BMD_TO_CTRL.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/pipe_1_lane_pci_exp_32b_app.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/s6_pci_exp_32b_app.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/v5_blk_plus_pci_exp_64b_app.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/v6_pci_exp_128b_app.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/v6_pci_exp_64b_app.v
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/implement/esults.bld
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/implement/implement_dma.pl
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/implement/implement_dma_backup.pl
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/implement/netlist.lst
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/implement/results/mapped.map
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/implement/results/mapped.mrp
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/implement/results/mapped.ncd
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD/common
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/implement/results
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/BMD
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga/implement
bmd_design/ipcore_dir/bmd_design/dma_performance_demo/fpga
bmd_design/ipcore_dir/bmd_design/dma_performance_demo
bmd_design/ipcore_dir/bmd_design
bmd_design/ipcore_dir
bmd_design

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