资源列表
Bus_Enable
- veilog小程序 参考设计中的 该程序说明了如何使用一个总线-veilog applet reference design of the program shows how to use a bus
BlackJack
- 本人利用FPGA实现的二十一点游戏程序，其中顶层电路用sch文件给出，每个模块使用VHDL语言编写-I use FPGA blackjack game programs, including the top-level circuit sch file gives each module using VHDL language
CoreFIR_RTL-3.0
- actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algori
I2s
- i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the implementation of custom I2C slave devices. The core provides a means to read and write up to 256 8-byte registers. These registers can be connected to the users
MP3-coder
- In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder. Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read t
AD9851
- 控制AD9851输出频率 控制AD9851输出频率 -control ad9851 frequence
2dpsk_mod
- 二进制差分相移键控调制的FPGA实现 采用Quartus原理图与VerilogHDL混合设计-Binary differential phase shift keying modulation with FPGA using Quartus mixed design schematic and VerilogHDL
2psk_mod
- 2psk调试的FPGA实现，Quartus完整工程-2psk debugging FPGA implementation, Quartus complete works
2fsk_mod
- 2FSK调制的FGPA实现，Quartus完整工程-2FSK modulation FGPA implementation, Quartus complete works
2ask_mod
- 2ASK调制的FPGA实现，Quartus完整工程。-2ASK Modulation Based on FPGA, Quartus complete works.
cordic
- 用Verilog写的CORDIC算法程序，经验证完全能实现-Using Verilog to write CORDIC algorithm, proven it can achieve the
verilog1024fft
- 1024点的fft快速傅立叶变换verilog代码-1024 point fft verilog code for Fast Fourier Transform