资源列表
CNT60
- 用VHDL设计了60的计数器，并用波形仿真验证了其功能-Design with VHDL counter 60, and a waveform simulation to verify its functionality
shujucaiji
- 数据采集系统用VHDL实现，把各个模块有机的结合起来，省去了单片机及其大量外围电路的连接-Data acquisition system using VHDL, the organic combination of each module, eliminating the need for a large number of single-chip peripheral circuits and connections
fsl_net
- 基于FSL总线的以太网控制器,用于Microblaze系统-Ethernet controller based on FSL bus
up3_board
- 关于UP3板开发的电子钟的最基本的功能 显示时间-About UP3 board developed the most basic functions electronic clock display time
PAL_TV_VGA
- 基于fpga de2平台pal制式tv实现-Pal standard platform based on fpga de2 tv realization
pmsmbased-onFPGA
- 基于fpga的永磁同步电动机的矢量控制教程，硕士论文-Fpga-based vector control of permanent magnet synchronous motor tutorial Thesis
fpga-sin
- 基于VHDL语言的正弦波形信号合成，含有仿真测试文件-Sinusoidal waveform based on VHDL signal synthesis, simulation test file containing
camera_test6
- 摄像头数据进行3*3表格的处理 然后进行中值滤波，8级流水线，速度快-Camera data for 3* 3 forms processing and then median filter, 8 lines, fast
code
- 32bit ripple adder, 32bit CLA code
TFT9325-SOPC-nios
- TFT9325的驱动学习，基于nios的源码-TFT9325 drive learning, based on nios source
XS3S1000
- XILINX公司XC3S1000FGG456下的VHDL工程,主要完成AD采用以及和CPU的数据交换-XC3S1000FGG456 s program example
ln
- vhdl写的自然对数计算，通过cordic迭代出的结果。提高精度需要增加迭代次数。-write vhdl natural logarithm, cordic iterate through the results. Improve the accuracy of the need to increase the number of iterations.