资源列表
ALU
- 8位ALU的设计，学习使用vhdl元件和包集设计-8-bit ALU design, learning to use vhdl components and package design
seqdet_5
- 本程序是5位序列检测器的Verilog源代码,已经过上机运行检测。-This program is five sequence detector Verilog source code, has been detected on the machine running.
fifo_ip
- 本程序是利用ise平台提供的IP核设计出的fifo，通过过上机运行检测。-This procedure is to use ise platform provides IP core design a fifo, passed through the machine running the test.
ram_ip
- 本程序是利用ise平台提供的IP核设计出的ram，已通过上机运行检测。-This procedure is to use ise platform provides IP core design of the ram, has passed the test on the machine running.
rom_ip
- 本程序是利用ise平台提供的IP核设计出的rom，通过上机运行检测。-This procedure is to use ise platform provides IP core design out rom, through testing on the machine running.
DE2_camera
- 通过摄像头采集图像显示到屏幕上，通过DE2开发板进行处理，基本实现显示功能。-Collected through the camera image is displayed on the screen by the DE2 board processing, the basic realization of display functions.
fsk
- 简单的FSK程序，并且经过了ModelSim检验-FSK simple procedure, and after a ModelSim test
FSK
- FSK（Frequency-shift keying）- 频移键控是利用载波的频率变化来传递数字信息。它是利用基带数字信号离散取值特点去键控载波频率以传递信息的一种数字调制技术。FSK（Frequency-shift keying）是信息传输中使用得较早的一种调制方式-FSK (Frequency-shift keying)- Frequency shift keying is the use of the carrier frequency to transmit digital inform
Verilog_HDl
- Verilog HDL是一种硬件描述语言（HDL:Hardware Discr iption Language），是一种以文本形式来描述数字系统硬件的结构和行为的语言，用它可以表示逻辑电路图、逻辑表达式，还可以表示数字逻辑系统所完成的逻辑功能。 -VHDL language is a high-level language for circuit design, digital systems primarily used to describe the structure, behavior,
8b10b_encdec_latest.tar
- 8B10B encoder VHDL code
Digital-Design
- Digital Design and Verilog HDL Fundamentals该书的所有代码，介绍了verilog语言的语法与基本硬件设计思路，有较好的学习借鉴意义-Digital Design and Verilog HDL Fundamentals book all of the code, introduced the verilog language syntax and basic hardware design ideas, there is good sense to le
ADDER8B
- 用VHDL描述了八位加法器，并通过波形仿真验证其正确性-Described in VHDL eight adder and verify its correctness by means of simulation waveform