资源列表
Odd-Frequence-Dividing-Circuit
- 一种奇数分频电路的设计方法，采用verilog HDL描述。修改代码中参数可以进行任意奇数分频，包含了设计文档和源代码。-A design of odd frequence dividing circuit is presented, which is described by verilog HDL。Change the parameter in code, one can get any odd numbers of frequence dividing circuit.
add4_fast_carry
- 一个4位超前几位加法器的设计，在modelsim中仿真通过。-This is a carry lookahead adder design, which is simulated successfully in modelsim.
FSM_3blocks
- 经典3段式有限状态的verilog HDL描述，在modelsim 中仿真通过。-A classical FSM of three paragrahs, which is described by verilog HDL and simulated in modelsim successfully.
ic2
- 一个IC2的verilog HDL设计，包含了modelsim的工程文件。-This is a IC2 design, which is simulated successfully in modelsim.
cordic_pipelined
- CORDIC算法的流水线verilog HDL实现，包含modelsim仿真所需的设计文件与testbench。-This is an implementation of CORDIC algorithm in verilog HDL, which contains design code and testbench.
16-bit-parallel-mult
- 16位并行乘法器， 由四个4位乘法器组成-16-bit parallel multiplier, consisting of four four multipliers
aaa-crall2
- UCI7701液晶驱动芯片控制程序，能够使其按照指定波形输出数据进行屏幕刷新，自带验证程序-UCI7701 LCD driver chip control procedures, to make it according to the specified waveform output data to refresh the screen, built-in validation process
filter_signed_and_unsigned
- FIR滤波器的verilog语言实现（输入为8bit有符号以及无符号两种，滤波器为8阶，截止频率约在6*pi/7）-FIR filter verilog language (input 8bit signed and unsigned are two 8-order filter cut-off frequency is about 6* pi/7)
FPGA---think
- FPGA思考笔记，思考FPGA背后的故事，深刻理解fpga，从此不再愁-FPGA thinking notes, thinking the story behind the FPGA, a deep understanding of fpga, no longer worry
jtd
- 简易交通灯的VHDL程序 采用模块化的设计思想 采用状态机的形式编写主要的控制模块-Simple traffic light VHDL program uses a modular design concept in the form of a state machine to write the main control module
FPGA应用开发入门与典型实例_源程序
- FPGA程序开发的基础入门程序，便于初学者更好的学习FPGA开发的流程
FPGA
- FPGA将68013传来的数据写入SRAM中-The 68013 FPGA SRAM write data coming in