资源列表
projectiverestore
- code to didvide the final output
ni677
- Including principal component analysis, factor analysis, Bayesian analysis, Pisarenko harmonic decomposition algorithm, PV modules contain, MPPT module, BOOST module, inverter module.
fpga
- 简单的键盘输入，点阵，数码管以及LCD显示(imple dot matrix, digital tube and LCD display)
py2cmod-0.1.2.tar
- this is a scoerboarding algorithm
Boyka Undisputed IV All-1538949-subdown
- sub down subtitle in verilog
rs485
- communication rs232 in vhdl with clock divider, counter, buffer, rs232tx, rs232rx.
verilog
- 8位计数器，可以实现计数器的相关功能，内涵verilog文件和testbench文件(8 bits counter,include v and testbech files ,has the ability of 8 bits counter)
natebege-0.2.0.tar
- wishbone vhdl config tool
vhdl_VGA
- Vhdl code for using screen (DE10-Lite)
CPU-Pipeline
- 五级流水线的CPU的工程文件，在vivado上用verilog语言实现，包括串口，可进行简单的数学加法运算。(Five-stage pipeline CPU project files, including the serial port. vivado Verilog language. This CPU can do simple mathematical addition.)
12864
- 通过C语言，用51单片机驱动12864液晶屏，使其能够显示图片(Through the C language, 51 single chip microcomputer is used to drive the 12864 LCD screen, so that it can display pictures.)
MIPS_IP
- MIPS IP,不用太多解释吧，大家都懂的-MIPS IP, without too much explanation, we understand about the