资源列表
VHDL2FSK
- VHDL 2FSK调制解调器各部分的原理与代码(The principle and code of each part of the VHDL 2FSK modem)
entrelacement-vhdl
- VHDL Implementation Interleaver
diver
- 用VHDL语言产生一个5位数除法器，电子课程设计题目之一-VHDL
uartfifo
- FPGA串口代码实现，带串口模块控制程序-Realization of UART in FPGA, with UART module control codes.
656to601
- 本程序实现视频图象的CCIR656转换CCIR601格式,使用的环境是Quartus II 4.0-the program CCIR656 video image conversion CCIR601 format, The environment is the use of Quartus II 4.0
Graphic-design-
- 基于QUARTUSII图形输入电路的设计 1、 通过一个简单的3—8译码器的设计,掌握组合逻辑电路的设计方法。 2、 初步了解QUARTUSII原理图输入设计的全过程。 3、 掌握组合逻辑电路的静态测试方法。 -Graphic design QUARTUS II based on the input circuit
lcd1602
- FPGA控制1602显示，内含vegilog程序-FPGA control 1602, the program includes vegilog
frenq2
- 数字硬件频率计 带有频率测量和占空比测量功能(Digital hardware frequency meter Frequency measurement and duty ratio measurement function)
shumaguandongtai
- VHDL的动态扫描显示六个数码管，包含分频代码产生25kHz的扫描信号作为时钟。-VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.
rs232_syscon_latest.tar
- 串口通信后处理程序，可以对收到，到的数据进行处理，来源opencore-After serial communication process, can be received, the data processing, source opencore
Electronic-Code-Lock-
- 基于Verilog的FPGA的电子密码锁的设计-Verilog FPGA-based electronic lock design, buttons with image stabilization
SRAMreadwritetest
- 这是用verilog开发的外部SRAM测试程序，编写了SRAM的读和写，当读写值相同则点亮LED。在实际测试中检测是正确的。对调试SRAM的朋友有一定的参考价值-It is the development of the external SRAM with verilog test procedures, preparation of SRAM read and write, read and write the same value when the light LED. In the act