资源列表
waveform_gen_latest.tar
- 波形发生器，用于编写testbentch文件。非常实用-Waveform generator, for the preparation of testbentch files. Useful
microwave-oven
- 这是个微波炉的VHDL程序，描述了定时，复位，倒计时等功能-It is a process of VHDL,describing microwave oven how to work
399
- 用VHDL编写的8位全加器,数字分频器等程序-VHDL prepared by the eight All-Canadian, digital dividers procedures
final
- 一个32位的cpu设计，实际是verilog语言，只不过pudn上没有verilog的选项，希望能对你有帮助-this is a 32 bit cpu designer project,which use verilog language. Hope it could help u.
8b_10b
- 8b_10b编码解码源码以及相应的测试文件基于14.2-8b_10b codec source code and the corresponding test file is based on 14.2
waveform_gen_latest.tar
- 这个核心是一个向前的实现数控振荡器（NCO）-也被称为直接数字频率合成器（DDS）。除了生成标准的正弦/余弦输出波形，它也产生平方和锯齿用很少的额外资源输出。-This core is a straight forward implementation of a Numerically Controlled Oscillator (NCO)- also referred to as a Direct Digital Synthesizer (DDS). In addition to genera
counter
- this is a counter this is a counter
xapp855
- FOR XILINX FPGA VHDL PROGRAMMING LVDS INTERFACE DEscr iptION
pingpangqiu
- 基于basys2的简单的乒乓球小游戏，通过ise13.4开发，使用语言VHDL，能够通过VGA在显示屏显示，能够实现双人对打，有计分功能。-Simple table tennis game, based on basys2 through ise13.4 development, using VHDL language, can through the VGA display shows, can achieve a double play, scoring function.
Count-of-29-hex
- 29进制的计数期，vhdl实现，在quartus里编译成功-Count of 29 hex, the VHDL implementation, compiled in quartus success
Faraday_rtl
- These designs were developed by Faraday Technology Corporation, a fabless ASIC vendor and silicon Intellectual property (SIP) provider in order.-Faraday Technology Corporation, a fabless ASIC vendor and silicon Intellectual property (SIP) provider in
lab7_adders3
- 加法器的verilog实现，第二种方法：超前进位加法器 -Another implementation of adder in verilog