资源列表
ct9999
- 很经典的数字钟程序CPLD / FPGA ，对初学者很有用。-Classic digital clock program CPLD/FPGA, useful for beginners.
demo6-BEEP
- 蜂鸣器实验，简单易懂，关于音节的资料可以上网查看，实验给出的方法适合初学者学习-Buzzer experiment, easy to understand information on the syllable can go online and read the experimental method is suitable for beginners to learn given
jiaotdengCPLD
- 这是一个用Verilog HDL语言编写的交通灯程序。可以用Quartus II运行。
seg7led
- 基于quartusII7.2的七段led试验程序，全面，丰富且完全通过功能验证-Led the team respectively quartusII7.2 based on testing procedures, comprehensive, rich and fully functional verification
sp3e1600e_mb_webserver
- VGA DRIVER FILES FOR FDPGA
de2_dac_lcd
- FPGA KIT DE2-35 This project outputs a selected voltaje using VGA DAC, the DAC module is controlled using LCD display and buttons.
m4kvgachar
- 基于M4K的字符VGA显示，来源于特权同学-M4K based VGA display characters, from the privileged students
10_100m_ethernet-fifo_convertor_latest.tar
- 10_100m_ethernet-fifo_convertor_latest,使用verilog语言写的，请需要的下来参考，不要用于商业，谢谢！-10_100m_ethernet-fifo_convertor_latest, using the verilog language to write, please refer to the needs of down and not used for commercial, thank you!
paobiao
- 基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙，秒，分。 有开始，暂停，复位功能。 学习VerilogHDL的经典例子，添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube sho
dds
- fpga利用dds原理，产生正弦波，简单实用，成本低-fpga using dds principle, have a sine wave
iic_verilog_ACK
- IIC_Verilog。考虑到了ACK(应答信号)，AT24C02（EEPROM）与EPM240的IIC通信，字节写选择读。在特权老师的基础上改的。经过这次更改后，对IIC时序有了很深刻热认识！ 代码自己验证过！-IIC Verilog AT24C02 with EPN240
Gratingthefoursegmentsandthedefensetothecircuit.ra
- 光栅尺的四细分和辩向电路,里面有样图可以之间看到-Grating the four segments and the defense to the circuit, which has kind of map can be seen between