资源列表
CostasLoop
- costas loop in vhdl -costas loop in vhdl ...
cordic
- we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentia
sdr-sdram-(verilog)
- Altera的SDR SDRAM模型，verilog实现，带说明书文件以及仿真文件、SDRAM原型文件。-Altera' s SDR SDRAM model, verilog implementation, with manual files and simulation files, SDRAM prototype file.
acquisem
- 利用FPGA超声TOFD焊缝探伤数据采集系统的设计-FPGA-based ultrasonic TOFD weld inspection data acquisition system
ct
- 用vhdl做的一个简单的太空大战游戏，在hdle实验板上可以运行，在16*16点阵可以显示飞行器移动，障碍物下落效果-Vhdl to do with a simple space war game, the board can run in the hdle experiment, in 16* 16 dot matrix to display the vehicle move, obstacles fall effect
Timer_sigtap
- 用Verilog HDL语言写一个计时器。其实就是在计数器的时钟输入端输入一个固定频率的时钟-Verilog HDL language used to write a timer. Is actually counter clock input of a fixed frequency clock input
CPU
- 用Verilog HDL语言写一个简单的处理器CPU。包括IR,Control unit,A,Addsub,G,Counter,8个寄存器。-Verilog HDL language used to write a simple processor CPU. Including IR, Control unit, A, Addsub, G, Counter, 8 registers.
verilog
- 介绍了一种64位子字并行乘法器的设计。根据不同的操作模式可以完成普通模式操作即64bit*64bit乘法操作，又可完成子字并行操作模式，即4个16bit*16bit乘法操作。-Introduced a 64-seat word parallel multiplier design. Depending on the operating mode Normal mode operation can be done that 64bit* 64bit multiplication operation
Verilog
- 无线通信FPGA 一书中的verilog代码- verilog core
VHDL-8259
- 用VHDL语言 实现8259A中断芯片的功能-VHDL language with the 8259A interrupt the function of the chip
pll
- quartusII环境下用Verilog语言的数字锁相环的实现。- In quartusII environment digital PLL implementation using Verilog language .
URISC
- 一个完整的带I/O和RAM，ROM的URISC,可以完成A+B/2的运算。实际上，通过对ROM的手工编程，可以实现8为数据的加减乘除，已经更加复杂的运算。-An ultimate URISC With I/Os, a RAM, a ROM,which can complete A+ B/2 calculations. In fact, through the ROM of the manual programming, it can do more calculations,such as A+