资源列表
SCRAMBLER
- 32位扰码器的verilog代码，编译通过-The Verilog code of 32_bit scrambler
BALANCEBALL-Finale
- 重力感应小球游戏，基于FPGA平台，Verilog语言，VGA输出。-Gravity sensing ball game, based on FPGA platform, Verilog language, VGA output.
count100
- 一个用VHDL语言编写的一百进制计数器。软件平台是Quartus II 7.2 ，由前面设计的小模块组合起来制作的，适合初学者，通过这些程序，刚接触VHDL的学习者可以一步步的去认识和了解VHDL，最后通过设计一个具有实用功能的电路，来增加学习者的成就感和学习兴趣。所有程序软硬件调试都成功通过，硬件平台是自己学校设计的一块开发板，要了解的可以联系本人。联系QQ：782649157 -Written in VHDL language using a binary counter 100. The
sram
- 基于FPGA的SRAM控制程序，里面附加了在线逻辑分析功能的程序，调试时相当的方便-SRAM-based FPGA-control program, which added an online feature of the program logic analysis, debugging very convenient when
chuzhuchejifeiqi
- 利用FPGA芯片控制出租车计费系统，采用Verilog HDL编写，程序简介-Control the use of FPGA chip Taxi billing system, using Verilog HDL preparation, procedures for
iir
- IIR50HZ的数字陷波器的FPGA实现-IIR50HZ digital notch filter implementation in FPGA
counter-CPLD
- CPLD学习，用VHDL,应用EPM7032,一个138，373和273的例程-CPLD study, using VHDL, application EPM7032, one of the routines 138,373, and 273
8bit_RISC_CPU_RTL_Code
- 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)
hdb3
- 这是一个很全的HDB3译码的verilog程序，用于FPGA入门所用，verilog的入门很好的程序-This is a very wide of the HDB3 decoding verilog program for entry-FPGA used, verilog entry procedures for good
clock
- 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
pulses_in
- VHDL实现两个脉冲间隔时间的检测，输出单位毫秒，测试成功。-VHDL realization of two-pulse interval of the test, the output units of milliseconds, the test successfully.
nios_led
- 基于FPGA的SOPC嵌入式的流水灯的实现。-Embedded FPGA-based SOPC flow light implementation.