资源列表
LEARNFPGA
- 学习FPGA的很好的材料，可以使你更深入的了解FPGA的关键技术-FPGA' s good to learn the material, can make you a better understanding of the key technologies FPGA
elevatorcontroller
- 用VHDL语言实现电梯控制器的设计，能够很好地实现功能，并且包含实验报告-VHDL elevator controller design,experiment report
dianziqin
- 用VHDL语言实现简易电子琴功能，并能播放歌曲，实验报告-VHDL,simple keyboard, play songs, laboratory reports
wujian7
- N=7基带信号发生器EWB实现,N=7基带信号发生器EWB实现-N = 7 base-band signal generator EWB realize, N = 7 base-band signal generator to achieve EWB
rtl
- 基于VERILOG的SDRAM控制程序，是目前主流设计方法-Control procedures based on VERILOG of SDRAM, is the main design
biaojue
- VHDL编写的七人表决器，有做课程设计的有福了-Written in VHDL seven voting machine, there are so blessed Oh curriculum design
Lab6
- 采用ISE10.1，VHDL语言数字时钟的设计，压缩包为源程序代码-By ISE10.1, VHDL language digital clock design, source code for the compressed
counter
- 用VHDL语言编写COUNTER-FPGA VHDL COUNTER
reference
- 自己做IC课程设计的成果，用Verilog语言进行编写的。 主要是基于IEEE802.3的交织和解交织。中间可能有在解交织的时候，信号有一些移位，最初编写的时候自己没有发现，注意用的时候改正下。 还有是一些的实际项目中的代码，很具有参考价值-These are our IC design curriculum outcome, written with Verilog language. It is mainly about the interleave and deinterle
de2sound
- 这个设计结合音频输入从麦克风和线路信号和输出结果线输出信号。麦克风连接话筒端口、音源线在端口,扬声器/耳机线端口。-This design combines audio input from the microphone and line in signals and outputs the result to the line out signal. Connect a microphone to the MIC port, an audio source to the LINE IN por
AtmelFPGAPwm
- atmel fpga pwm implimentation docs
logic
- 多通道扫描AD控制逻辑。Verilog语言编写-AD control logic multi-channel scanning