资源列表
VHDLAMSandMAST
- a useful document for VHDL-AMS and MAST languages
vhdl_Quick_Reference_Card
- vhdl quick reference
vhdl_cookbook
- The VHDL Cookbook First Edition
vhdl-tut
- Writing VHDL for RTL Synthesis
advanced_FPGA_Design
- Advanced FPGA Design Architecture, Implementation, and Optimization
dds_vhdl
- fpga VHDL语言，控制DDS产生频率可变的正弦波信号扫频-FPGA VHDL DDS
52_divider
- 多倍（次）分频器 请注意: 本例的各个源描述的编译顺序应该是: 52_divider.vhd 52_divider_stim.vhd-Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd
IIC_Verilog
- FPGA Verilog HDL模拟IIC通讯接口-FPGA Verilog HDL IIC Interface
airconditioner
- 中央空调的控制，3级控制系统，这个是中间控制的vhdl源代码-Central air-conditioning control, 3 control system, this is the middle of the control of vhdl source code
sui
- 应用硬件描述语言产生随机数，在模糊控制仿真中应用的较多-By VHDL generating random Numbers, in the application of the fuzzy control simulation
telephone
- 利用verilog语言设计公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块-The use of public telephones were verilog language design include the following states: hang up, standby, identification, change passwords, call the five states. Includes a detailed
QBB_SMALL_CPLD-32X512--2009-09-04
- 实现大型LED屏显示的CPLD程序，对FPGA学习很有帮助-To achieve large-scale LED screen display of the CPLD program, very helpful for learning FPGA