资源列表
DecoderSync
- 本程序用来分离出行同步，列同步和场同步信号，分离后可以得到Hs,Vs和，Fs三个同步信号-This procedure is used to separate travel synchronization, the column sync and field sync signals can be separated Hs, Vs, and, Fs 3 sync signal
recuart_50m
- 串口发送: 使用串口发送程序接收二进制码（9600波特率） ，用拨码开关控制发送二进制的高四位，按板上的第二个按钮，LED灯会相应的亮起，PC 会收到相应的数据-Serial port to send: Use the serial port to send a program to receive a binary code (9600 baud), with DIP switch control to send binary high-4, according to board the
S6_VGA
- 利用cpld作为控制器实现驱动vga显示器，虽然只有8位色，但是实现方式只得借鉴-cpld verilog vga
VGA_test50m
- VGA显示: 连接显示器到开发板显示器接口，显示器会显示 640x480 的彩条 -VGA Display: Connect monitor to the development board display interface, the display will show the color of 640x480
senduard_50m
- 串口发送: 使用串口发送程序接收二进制码（9600波特率） ，用拨码开关控制发送二进制的高四位，按板上的第二个按钮，LED灯会相应的亮起，PC 会收到相应的数据-Serial port to send: Use the serial port to send a program to receive a binary code (9600 baud), with DIP switch control to send binary high-4, according to board the
fftip
- Quartus中fft ip core的使用-Quartus in the use of fft ip core
KM
- vhdl code 16 bit processor
EPM7128_flash_config_controller
- Using the Nios Development Board Configuration Controller Reference Designs
Taximeter_VHDL_procedures
- 出租车计价器VHDL程序，包括时序仿真图-Taximeter VHDL procedures, including timing simulation diagram
DAC0832
- DAC0832 接口电路程序，产生频率为762.9Hz的锯齿波-DAC0832 interface circuit process, resulting in the sawtooth frequency of 762.9Hz
URAT_VHDL
- URAT VHDL程序与仿真，包括顶层程序与仿真，波特率发生器VHDL程序， UART发送器程序与仿真，UART接收器程序与仿真-URAT VHDL procedures and simulation, including the top-level procedures and simulation, VHDL program baud rate generator, UART transmitter and simulation program, UART receiver and simu
base-band_code_generator
- 基于VHDL硬件描述语言的基带码发生器程序设计与仿真，基于VHDL硬件描述语言，产生常用基带码-VHDL hardware descr iption language based on the base-band code generator program design and simulation