资源列表
FRE
- 用1602显示的等精度频率计，有多种功能的；可能测试占空比和周期的-vhdl
reedsolomon
- reed solomon encoder synthesis and simulation is done using verilog and working fine
ddsm
- 用vhdl实现dds功能的程序试一试看看是不适合你！-Dds feature using vhdl program to try to achieve a look is not for you!
uart
- uart-universal aynchronious reciever and transmitter used to connect the pc and fpga to pass the data
Verilog
- altera公司推荐的verilog代码风格教程-altera recommended verilog code style tutorial
f_adder_4bit
- 四位二进制全加器，用原理图输入的形式实现，在Quartus II 5.1下编译通过。-4 binary full adder, with schematic input in the form of implementation, compiled in the Quartus II 5.1 adoption.
show_numbers
- 在八位七段数码显示管上显示8位学号，要显示的学号可以在程序内改。-In the eight seven-segment digital display tube display 8 Student ID, Student ID to be displayed can be changed within the program.
double_shifter6
- 带置位的双向移位串入/并出6位移位寄存器。-With a string of set-bit bi-directional shift into/and a 6-bit shift register.
ADC0809
- 完整ADC0809的时序，采用VHDL语言编写，在Altera cycloneI/II系列下的EP1C6\EP2C5\8平台下测试完成，稳定-ADC0809 Driver by VHDL
ele_clock
- 时钟（时分秒LED显示） 秒表（计时） 闹钟（自动报时）-alarm clock
ctrller
- 本代码是控制SDRAM的VHDL代码，几经优化现已趋近完美，里面主要用状态机实现，现封装为entity，便于调用模块-This code is to control the SDRAM of the VHDL code, optimization has been several times closer to perfection, which is mainly used to achieve a state machine is encapsulated entity, easy to c
VHDL
- 基于vhdl数控分频器的设计与应用，少有的关于分频方法的介绍-Divider based on vhdl design and application of NC