资源列表
ETH_SRC
- 网络接口源码实现，使用的是Verilog语言-ethernet Verilog
videocap
- 基于FPGA的视频采集源程序，完整代码，以供参考-FPGA-based video capture source, the complete code for reference
Experiment08
- FPGA源码，供初学者使用，时钟化和信号长度-GA source code, for beginners, clock and signal length
ppt4aix4sopc
- 基于AXI4的sopc开发讲义,2011年电子大赛的辅导材料-powerpoint for aix4 sopc development
cpld_uart_TXRX
- max2 cpld 开发的vhdl 完整串口通信程序，TXRX可同时收两个命令 带超时 600门-max2 cpld vhdl developed complete serial communication program, TXRX can simultaneously receive two commands with timeout 600
d_e_g_dds
- 基于Verilog HDL的迟早门码元同步方案中的DDS程序，已经仿真通过，可以在FPGA开发板上实现。迟-早门方式实现码元同步在无线通信中有着广泛应用。来自华中科大。-Early-later gate of Verilog HDL-based symbol synchronization scheme in the DDS program, has been through simulation, can be achieved in the FPGA development board. F
DE2_Basic_Computer
- Convert DE2 FPGA to Small Computer
audio_project
- Enhanced Audio Project by Dixie Xue & Wei Zhang -Enhanced Audio Project by Dixie Xue & Wei Zhang
Books
- This book emphasises on the concept of C
cpu-and-ram
- 这是一个用VHDL语言写的简单带存储器的CPU设计，不涉及流水线设计，只是简单的利用QUARTUES II里的ram-This is a simple memory write VHDL CPU design, does not involve the assembly line design, simply use the ram in QUARTUES II
i2c_master_slave_core
- I2C接口的主从模式代码,独立的IP，可以快速嵌入到自己的设计项目！-Master I2C interface code from the model, independent of IP, you can quickly embed into their design projects!