资源列表
For_student_demo
- verilog HDL编写的音乐程序和加法器程序 -The music and adder program files by verilog HDL
vhdl
- 几个VHDL的源码小程序，对学习硬件描述语言很有用的哦 ！-VHDL source code a few small procedures, hardware descr iption language learning useful Oh!
dcm
- Xilinx的V4FPGA数字时钟管理模块的底层原语实现代码，硬件上跑通- The Xilinx V4FPGA digital clock administration module s first floor primitive realizes the code, on the hardware runs passes
eda
- 用verilog硬件描述语言编写的电子琴工程，实现手动弹奏21个音符，自动播放内置音乐，在显示器上模拟显示按键等功能。-Using verilog hardware descr iption language organ works, play 21 notes for manual, automatic built-in music player, analog display buttons on the monitor and other functions.
Xilinx_constraints.pdf
- detail timing constraint for Xilinx FPGA design
1day11-keyboard
- 清华大学电子课程设计：Verilog语言编写，可在QuartusII完全正确运行，FPGA下载，键盘按键输出相对应数字，有防抖功能-Verilog language, can be run in QuartusII entirely correct, FPGA download, keyboard keys corresponding to the output figures, anti-shake function
DSCH2
- VLSI compiler or nano chip designer.
Verilog超详细教程-北京大学于敦山
- Verilog超详细教程，北京大学于敦山(Verilog Course Peking University)
CORDIC
- 基于VHDL语言的CORDIC算法，长度为32位-CORDIC algorithm based on the VHDL language, length 32-bit
counterFastSlow
- 完整vhdl计数器，多种功能。 stop/ en/ fast/ slow/-Complete vhdl counter, a variety of functions. stop/en/fast/slow /
verilog
- Velilog大学教程PPT的PDF版本(The PDF version of the Velilog University tutorial PPT)