资源列表
spi_slave_lattice
- 这是基于lattice fpga 做的spi slave模块。简单易懂，适合初学者。代码使用状态机描述。整个工程在diamond2.0版本编译运行。-This is based on lattice fpga do spi slave module. Easy to understand for beginners. The code using a state machine descr iption. The whole project is run diamond2.0 version o
xinhaofashengqi
- 基于FPGA，QUARTUSS||开发环境下的可调信号发生器的实现，可产生四种波形-Based on FPGA, QUARTUSS | | development environment to achieve adjustable signal generator can produce four kinds of wave
cpu
- 用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the f
usb_veriloghdl
- USB是 FPGA设计，verilog语言实现(USB is FPGA design, Verilog language implementation)
frequency_generator
- frequency generator veriolg code
Decoder3x8
- 把2x4解碼器再擴展為3x8解碼器,可控制8個LED掃描電路的驅動-The decoder then extended to 2x4 3x8 decoder can control eight LED driving scanning circuit
V4_Verilog_programming
- 这个文档是V4的verilog编程手册，齐全而实用。欢迎下载。-This document is the V4 programming verilog manual, complete and practical. Welcome to download.
OK-fifotest-important_low_to_high
- 高速到低速的FIFO乒乓操作，已经测试通过-Achieve the pingpang operation of FIFO
par_in_par_out
- 并入并出双向移位寄存器，很好很强大。使用Verilog进行设计并用Modelsim成功仿真。-Into the shift register and a two-way, very very strong. With Verilog for design and simulation using Modelsim successfully.
Example-b3-1
- 复杂的可编程逻辑器件硬件编程语言实例先进先出范例-The stuy of VHDL language
v5_config
- xilinx v5的在线，上位机配置程序-xilinx v5 configuration
cpu
- 用FPGA实现了CPU中RAM,ROM等功能，设计比较完整-FPGA Implementation of a CPU, RAM, ROM, function, design is more complete