资源列表
music_player
- 音乐播放器，基于verilog硬件描述语言实现音乐播放器功能。-music player
EP2C
- EP2C8核心板电路图，对设计FPGA电路有帮助。-EP2C8 core circuit board, FPGA circuit design help.
picoblaze_test_700AN
- Xilinx PicoBlaze application developed in ISE10.1.3.
XuexiCPLD
- 学习CPLD的入门教程，内容简单、精彩，教你一步一步学习CPLD-Introductory tutorial to learn CPLD, the content is simple, exciting, teach you step by step to learn CPLD
s3esk_picoblaze_nor_flash_programmer
- 利用picoblaze微控制器对Intel flash进行控制，实现了flash的读写，擦除等基本操作-picoblaze Microcontrollers use of Intel flash control, realized the flash write, erase and other basic operation
11
- 等精度频率计，verilog语言写的，可在开发板上验证，已经试过-And other precision frequency meter, verilog language, and can be verified on the development board, has tried
贪吃蛇
- 都是废话电视剧方法那就回家避难硐室不烦你(dshdjsdhdhfjdskfk nbkjknl)
FPGA实现贪吃蛇游戏用VGA显示
- FPGA实现贪吃蛇游戏用VGA显示游戏，quartesII实现源代码，整个工程文件直接运行
C6416DSK
- dsp图像处理程序 imlib库等的使用技巧-DSP image processing program imlib library use skills
lab6
- 有关加法器的操作处理，内涵简单加法器一直到八位带进位加法器编程，附有word文档描述-Related to the handling of the operation of the adder, the connotation of a simple adder to the eight into the adder programming attached word document describes
VGA_disp
- clk divid 模块为分频电路，对50MHz 系统时钟进行分频产生50M/7Hz 的像素时钟。VGA control 模块为VGA 显示控制电路模块，在像素时钟的驱动下首先产生行频信号，而后对行频信号进行分频产生58Hz 场频信号。由于VS 与HS 信号具有严格的时序匹配，即VS 信号必须为HS 信号的整数倍，以保证在场频信号有效期间，能够完整数行的扫描，本设计利用对行频信号进行计数分频来产生场频信号。-Clk divid module for the frequency circuit,
jiyufpgadeshipingcaijichengxu
- 能够很好地进行视屏采集程序，是基于fpga的vhdl语言编程-Can be a good screen capture program, FPGA-based VHDL language programming