资源列表
DDS-320-modu
- 在采用 320x240 屏的设计实验箱上运行，产生正弦波，调幅调频波形，扫频。
uart_test
- 用verilog实现的一款232协议的源码，支持光纤传输，IO通道传输等等传输方式。(Verilog implementation of a 232 protocol source code, support fiber transmission, IO channel transmission and so on transmission.)
dual_priority_encoder2
- 这是一个组合电路，实现的是8位的优先编码器。-this is a combination circuit,Implement the eight priority encoder，
ILI9221DS_V0.5.RAR
- ILI9221 LCD datasheet
sramfiles
- VHDL Interfaces and Example Designs
EDAandVHDL4
- 包含本系列的第四部分内容，详细介绍了VHDL如何编程，包括VHDL的语句和结构，举例丰富。-The fourth part of this series contains the contents, detailing how VHDL programming, including statements and structural VHDL, for example rich.
mydds2
- 利用dds产生产生正弦余弦信号的代码，利用的是rom的方式-Generating code using dds sine cosine signal, using the way of rom
draw_char_type
- FPGA字符显示控制，RAM作为显存地址存放现在内容，ROM作为显示字模。-FPGA character display control, RAM memory address is stored as the content now, ROM as a display font.
oc8051_verilog
- 兼容8051的内核oc8051，verilog版本的-8051-compatible core oc8051, verilog version of
Xilinx-design-timing-constraints
- 很有用的Xilinx时序约束设计资料，很适合初学者-Very useful Xilinx timing constraints, design data, is very suitable for beginners
freq_meter
- 使用verilog写的频率计，可切换档位-Frequency counter using verilog write switch stalls
i2c_core
- i2c ip core support slave and master mode