资源列表
STATE5
- VHDL源代码程序，使用VHDL语言编写，米勒，莫尔型状态机
hdb3
- hDB3的编解码模块 是在maxplusII 下验证过的 并且下到片子中都正确
4
- simple code based on verilog shifter , cla ,clg , ALU , PC
code
- modelsim下的60进制计数器源码和测试激励文件-modelsim M counter 60 under the source file and test incentives
coslist
- cos表值寄存器，1024点，10位地址，10位数据-the list of cos，1024 points，10 bits of address, 10 bits of data
PCB_Project1.~(1).PrjPCB.Zip
- 51MCU & CPLD EZ-KIT实验开发板--
pidviaVhdl
- VHDL实现PID发动机转速控制,内置程序说明，一目了然-VHDL realize PID control engine speed, built-in program instructions at a glance
iso14443
- 13.56MRFID__iso1443协议__NIOS II的实现-13.56MRFID__iso1443 agreement __NIOS II implementation
iic
- 我自己写的verilog ，实现iic总线的协议，分为带存储和不带存储两种。内部有测试代码程序，用modelsim仿真通过的。谢谢大家。-I write verilog, to achieve iic bus protocol is divided into storage and without storage with two. Thank you.
mmuart_latest.tar
- uuart 串口的verilog 源码实现，欢迎下载使用. uart 串口 verilog-uuart serial verilog source implementation, welcome to download
UART
- 基于FPGA器件和其他器件的UART通信，使用VHDL代码。-FPGA devices and other devices based on the UART communication, the use of VHDL code.
rsa_top
- rsa的顶层代码（用verilog编写，已编译）-the rsa the top level code (written in verilog compiled)