资源列表
4x4的数据选择器
- 用vhdl的4x4的数据选择器，在maxplusII下编译、仿真通过。是构成大型数字电路的重要部件。适合vhdl初学者分析学习。-4x4 with the VHDL data selectors, under the maxplusII compiler, simulation through. Yes constitute large-scale digital circuits important components. VHDL Analysis for beginners to lear
fpga1394
- 这是一段控制1394芯片的cpld的verilog程序,可以参考,在实际项目中已经采用.-This is a control chip cpld 1394 Verilog the procedures, they can refer to the actual project has been adopted.
electronic_watch
- 电子表仿真，有显示年月日、显示时间、修改年月日、修改时间、闹钟功能-electronic watch. Function: show of data, time, modification of data and time, and set alarm clock.
13
- para13： fifo.vhd FIFO（双口RAM） fifo1.vhd FIFO（嵌入式EAB） fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
I2C0001
- 基于FPGA的I2C程序0001,很不错的论文及程序，，大家快下啊-FPGA-based procedures I2C 0001, a very good paper and procedures, we quickly under ah
16876
- C routine for LED (PIC16F876)
CU
- Unit Control with 8 bits at vhdl verilog code
Loadshedding
- This is a project using FPGA for implementing the preferential loadshedding schemes.
DDS-pulse-random
- 数字频率计，该代码可用于产生任意频率的脉冲-this code is used to generate pulse
DDS
- 数字频率计 DDS，使用Verilog编写-Digital frequency meter DDS, prepared using the Verilog
3
- 序列检测器。用于检测一组由二进制码组成的脉冲序列信号，在数字通信中有着广泛的应用。当序列检测器连续收到一组串行二进制码后，如果这组码与检测器中预先设置的码相同，则输出A，否则输出B。由于这种检测的关键在于正确码得收到必须是连续的，这就要求检测器必须记住前一次的正确码以及正确序列，直到在连续的监测中所收到的每一位码都与预置的对应码相同。在监测过程中，任何一位不相等都将回到某一状态（并不一定是初始状态）。-Sequential detector
control
- 北京邮电大学数字电路实验乒乓球游戏机设计；共有个五个模版，分别编写，最后综合在一起-Beijing university of posts and telecommunications digital circuit experiment table tennis game design There are five a template, separately written, and finally integrated together