资源列表
EDA_jiaotongdeng
- 《数字电路EDA入门－VHDL程序实例》---交通灯程序例子-"digital circuit EDA portal-VHDL program examples" -- traffic lights procedures example
397474fpq1281
- 自己编的一个分频器的程序模版 虽然原理很简单，经过多次实践很实用 被多次用在其它的程序中-own series of the dividers of a procedure template Although very simple principle, after repeated practice by many very practical use in other proceedings, and,
UART_VERILOG
- 该程序实现在ALTERA FPGA 上使用VERILOG HDL语言实现串口通信。-The program in ALTERA FPGA VERILOG HDL language used on serial communication.
Demo_19264
- 19264LCD的驱动程序，有必要的朋友可以-19264LCD drivers
fenpin
- 使用硬件描述语言设计的分频器，现代逻辑器件-Using hardware descr iption language design divider, modern logic
Air-conditioning-state-machine
- VHDL语言编的一个空调控制系统。cpld实验中的代码-VHDL language a series of air-conditioning control system. the cpld experiments code
vhdl00101
- vhdl源程序，对大家学习VHDL一定会有帮助！-VHDL source code, the right to study VHDL will be helpful!
bank_manage
- 实现自动排队并完成叫号，设置一个排号按键，以及四个柜台用消号按键。当按下叫号键时，1.若队列不满，LCD显示"Your No.is 01!"的字样。2.若队列已排满，LCD显示"The queue is full,please wait"的字样。当按下消号键时，1.若队列无人，LCD显示"Sorry,the queue is empty!"的字样。2.若队列有人，蜂鸣器响，LCD显示如"No.01 come to No.1window,please!"的字样。-Automatic queuing
clock
- verilog编写的8位数码管时钟，可现实秒，分，时-8 digital tube clock written in verilog reality of seconds, minutes, hours
STATE2
- VHDL源代码，使用VHDL语言编写，莫尔型状态机
fpgaaverilogamaxamin
- verilog 编写的比较最大值最小值得的程序，而且能够求出最大最小值在ram中存储的位置，测试通过下载即用-Comparison of the maximum write verilog smallest worthwhile program, and minimum and maximum values can be obtained is stored in ram position, the test that is used by downloading
SRAM6bit
- sram 6bit仿真模型，verilog编写-sram 6bit simulation model, verilog prepared