资源列表
FPGA_USB
- FPGA与USB通信的Verilog源码，希望对大家有用！-FPGA and USB communication Verilog source code, I hope useful for all of us!
exp_cnt_xuehao365_7seg
- 计数器 数码管 3位十进制 exp_cnt_xuehao365_7seg.vhd为顶层文件-Counter digital tube three decimal exp_cnt_xuehao365_7seg. VHD for top level file
test_work
- FPGA基本的常用模块，适合初学者了解基本的语言构成-FPGA basic common modules, suitable for beginners
AD80305
- 一种基于xilinx FPGA S6,verilog 实现AD80305输入输出接口配置，可参考-Based xilinx FPGA S6, verilog realize AD80305 input and output interface configuration, refer to
99341857matlab
- FFT algorithms FFT, IFFT, power spectrum calculation, including the Hamming window, Hanning window, triangle window, Blackman window, 4 term Blackman-Harris window of several of the power spectrum window function computing power.
tec_control_pgfa.rar
- 使用fpga基于积分分离的pid算法进行温控的程序，经实验证明很稳定,Fpga points based on the use of separate pid process temperature control algorithm, the experiment proved to be stable
VHDLdesignURA
- 用VHDL编写的URAT程序，适合教学或自学使用-VHDL URAT prepared by the procedures for the use of teaching or self -
addr4
- 可以实现四位全加器，使用四个全加器串联的方式，不是快速进位位的方式-Can achieve four full adder, full adder using four series were not as fast carry bit of the way
汉明纠错码译码器源程序
- 汉明纠错码译码器的VHDL源程序
raster
- 这是一个计算机生成图形图像的过程中，最重要的光栅化阶段的verilog代码。-This is a computer-generated graphic images of the process, the most important stage of rasterization verilog code.
fir_parall
- 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), throu
pc_cfr_test_v3_1c
- 一个关于降低现代通信系统中高峰均比信号的matlab算法，对于研究数字预失真基于FPGA实现的有一定作用！-A modern communication system on the lower than the peak signal matlab algorithm for FPGA-based study of digital pre-distortion to achieve a certain effect!