资源列表
DE2_70_pin_assignments.rar
- de2-70的引脚配置文件，给各位急需分享一下，用于fpga的开发,de2-70 of the pin configuration files, to share that much-needed for the development of fpga
ANALYSIS-OF-FULL-ADDER
- DEscr iptION OF FULL ADDER
shangchuan
- 几个基于VEGA的小程序 供大家参考学习-A small number of VEGA-based procedures for your reference study
ledBanner
- This a verilog code for ledbanner. Ledbanner uses Seven segment display and will shift number display 0 up until 9 or vice versa. It is done through the use of clock input, reset botton and the direction botton. when the botton is unpressed, 0 - 9 wi
TLC5510-VHDL
- （1）UART发送器VHDL程序 --文件名：transfer.vhd。 --功能：UART发送器。 --说明：系统由五个状态（x_idle,x_start,x_wait,x_shift,x_stop）和一个进程构成。 -(1) UART transmitter VHDL program- the file name: transfer.vhd.- Function: UART transmitter.- Descr iption: The system consists of
stopwatch-programmer-
- 秒表 stopwatch verilog语言编写-stopwatch verilog
calculator-horse-race
- 共3个程序，跑马灯，3位计算器，3-8译码器-Three programs, marquees, three calculators, 3 to 8 decoder
INIT-AND-CMD-FSM.vhd
- INItialization and command for double data rate
QD_Tft43
- cpld+sram驱动tft 驱动4.3寸480x272分辨率的tft显示屏-Cpld+sram drive TFT drive 4.3 inch 480x272 resolution TFT display
mips
- cpu---risc---mips源代码-cpu---risc---mips
1
- 计数显示电路。由十进制计数器模块（BCD_CNT）、分时总线切换电路模块（SCAN）和七段显示译码器电路模块（DEC_LED）构成。输入端口为为十进制计数器时钟clk，异步复位清零信号reset，分时总线切换电路时钟clkdsp。在reset信号为1时，电路复位不工作；在reset信号为0时，在每个clk的上升沿计数器将加1。在每个clkdsp的上升沿将会改变对三个数码管的扫描选通。输出端口为数码管选通信号sel（两位），输出到七段数码管的数据信号ledout（七位）。-Count displa
flashvhd
- 用FPGA编写的三星k9系列flash读写擦出程序-Samsung the k9 Series flash reading and writing struck a program written using FPGA