资源列表
NIOS_DIG
- 基于FPGA软核系统，通过nios编程使开发板数码管定时计数-FPGA-based soft-core systems through programmed to nios development board digital timer count
VHDL-ASK-MODULATE-AND-DEMODULATE
- 基于VHDL的ASK调制与解调设计与实现-ASK modulation and demodulation VHDL Design and Implementation
DE1-SoC_User_manual
- DE1-soc使用说明书，详细的介绍了DE1的硬件配置，使用方式-DE1-soc manual, a detailed descr iption of the hardware configuration DE1 of use
FPGA
- FPGA/CPLD数字电路设计经验分享 适合初学者-FPGA/CPLD digital circuit design experience to share
AD_4-
- ADC，芯片AD7812的转换代码，可实现AD转化，AD芯片用的是AD7812，实现16位数模转化-Verilog HDL code, the AD conversion can be achieved. AD-chip using a AD7812
osh
- Verilog开发脚本文件，Cyclone四代引脚分配源文件-Verilog development scr ipt file, cyclone pinout four generation file
Quartus_II_11.0
- QuartusII.11.0学习与应用，QuartusII.11.0的入门学习与快速应用方法-QuartusII 11.0 learning and application, QuartusII 11.0 introduction to the study and application methods quickly
IIC
- 使用verilog HDL编写IIC代码，通过FPGA读取mpu6050数据，其他IIC器件代码类似-IIC written using verilog HDL code, read mpu6050 data through FPGA, similar to other IIC device code
AD9910_div_clk2p5(1)
- AD9910在DE2板上实现单音信号点频-AD9910 DE2 board to achieve the tone frequency signal points
clk_div_3
- 利用Verilog语言实现3分频，在Quartus中调试通过！-Use Verilog language divide by 3, in Quartus debugging through!
traffic
- 用Verilog语言实现了一个路口四个方向的交通灯控制，并带有倒计时显示-Verilog language used to control traffic lights at an intersection of the four directions, and with a countdown display
zidong_led_water
- 用Verilog语言实现了将50MHz时钟分频到1Hz，实现了自动流水显示HELLO字母功能-Verilog language of the 50MHz clock frequency to 1Hz, realized the function of automatic water display HELLO letters