资源列表
RESOLVER
- 旋变位置信号的监测，cpld verilog-Monitoring resolver position signal, cpld verilog
new-data
- 磁阻式旋变的cpld处理，xilinx，抛砖引玉-Cpld processing reluctance resolver, xilinx, initiate
2012CPLD
- CPLD处理双旋变的程序，与单旋变类似，可以参考下-CPLD with a double spin transition program, similar to the single resolver, you can refer to the following
hdl
- 一个VHDL的小文件，经过测试可以使用。-A VHDL small files, the test can use,,,,
independent
- security gate controller
DDRController
- DDR3控制器，用于FPGA内部对DDR进行操作，利用Avlone总线进行对接-DDR controller
iicmax
- 基于verlog语言的iic程序，非常实用的IIC程序，适合刚入门的学习-dkjfaldjfakdj faldjfa dkjfa ldjfakdjlaj dkja dlfja lfjalkjdkajdkj dkjad dadfadsd
VHDL-code
- 使用VHDL语言进行门电路，优先编码器，译码器，各进制计数器，数码管显示的编写，在QUARTUS ii上模拟可用-Gates using VHDL language, priority encoder, decoder, each binary counter, write digital display, analogue available on QUARTUS ii
FPGA-frequency
- 本设计基于FPGA设计等精度频率计，并采用NIOS II控制液晶显示器显示测量频率。-The design is based on FPGA design precision frequency meter, and using NIOS II controlled LCD display shows the measured frequency.
MAC_TxScheduler
- Ethernet MAC-MII interface of Transmit
MII_RxMAC
- Ethernet MAC-MII interface of Receive
DE2_Default
- DE2开发板的默认开机程序，经过实验，完全正确，直接可以使用-DE2 board verilog program of start, it is very good useful