资源列表
image-new
- this coding is very effectively used for the image compression technique in vhdl
Verilog-Accumulator
- the folder contains two files written by Verilog HDL. the first one is an implementation of an accumulator that takes serial data as an input, and its output will be an accumulated sum of each consecutive four input samples. the second file is a te
booth_mul
- Booth multiplier used for multiplication of 2 s complement numbers in digital design by using booth multiplier we can reduce the partial products by encoding bits in the multiplier and perform the operation according to the encoded results on multipl
Crack_QII_13.1_Windows
- quartus 13.1 的破解文件 最新版本的破解文件-quartus 13.1 crack file latest version of the crack file
Crack_QII_13.1_linux_ALL
- quartus 13.1 linux 的破解文件 最新版本的破解文件-quartus 13.1 linux crack file latest version of the crack file
textiowrite
- quartus ii 环境下，一个完整的利用TEXTIO仿真的源代码，包括读数据文件和输出数据到文件。-Under quartus ii environment, a complete simulation using TEXTIO source code, including reading data files and output data to a file.
chapter4_fsk_2
- 2FSK调制模块，包括了仿真文件.当输入为1时，输出载波1，当输入为0时，输出载波2-2FSK modulation module, including a simulation file when input is 1, the output carrier 1, when the input is 0, the output carrier 2
Verilog-code-for-multiplier
- VERILOG CODE FOR 16 BIT MULTIPLIER USING MODIFIED BOOTH ALGORITHM
FILTER
- VERILOG CODE FOR 1D FIR FILTER IMPLIMENTATION -VERILOG CODE FOR 1D FIR FILTER IMPLIMENTATION
2D-FILTER
- VERILOG CODE FOR 2D FIR FILTER
filter_2d
- XILINX ISE FILE FOR FPGA IMPLIMENTATION OF 2D FIR FILTER USING MODIDIED BOOTH ALGORITHM
FFT
- VERILOG CODE FOR FLOATING POINT 8 POINT FFT