资源列表
two_d_dct_serial
- 二维DCT变换，采用查找表的方法实现算法，分别通过列变换，再通过行变换，通过加法器乘法器以及流水线技术得出更快的结果！-two-dimention DCTtransform,the algorithm was implemented by look up table,via row trasforming and colum trasforming respectively
ss
- DE2开发板 sopc开发例程 友经科技提供-DE2 development board sopc the development of science and technology provided by the Friends of routine
AlteraCycloneIIFPGAStarterBoard
- Altera Cyclone II FPGA Starter Board原理图-Altera Cyclone II FPGA Starter Board Schematic
carrysel_adder_files
- This has code of carry select adder.. It is written in VHDL.. Hope its useful for beginners .. All the best-This has code of carry select adder.. It is written in VHDL.. Hope its useful for beginners .. All the best..
santhosh_multiplier
- This has verilog code for multiplication.. It will be useful for beginners of verilog.. The testbench for multiplier is also attached with the file setup. Comments are welcome
santhosh_verilog_adder
- This has code off multibit Adder. IT is written in verilog. The associated test bench for the verilog code is also attatched within the rar file. Uncompress the rar file and the file name describes the function of each code file.. Comments are we
verilog_m
- 用verilog生成的m序列，包含四个.v的文件-verilog m sequence
SOPC_module
- sopc 常用模块 LCD_Delay LCD_EN delay_reset_block filter_200us-sopc module LCD_Delay LCD_EN delay_reset_block filter_200us
nios
- altera ep2c8V2 开发实例 timer uart I2C key interrupt 等-altera ep2c8V2 examples timer uart I2C key interrupt etc.
15-IP-core
- 15个免费的IP核 IP核源代码 -15 IP cores
rafal2
- VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
Verilog
- 这是VERILOG HDL的比较常用器件的源代码，包括寄存器、移位器-This is a comparison of VERILOG HDL source code commonly used devices, including registers, shifter, etc.