资源列表
Modelsim_chinese
- 介绍Modelsim的一个很好的中文教程，初学者可以通过它简单的了解其基本操作等相关知识-Modelsim introduced a very good English course, beginners can learn through its simple operation of the basic knowledge
SintaxisBasicaVHDL
- VHDL introduction basic and sintaxis
timer
- 计时器的Verilog描述 CPU设计者可以借鉴 -Verilog decription of the timer in processors
I2C
- I2C主机端模块 具有avalon-MT总线接口 可挂载在Altera soc系统之上 使NiosII处理器具备I2C通信能力 模块由Verilog HDL编写 并经Cyclone II FPGA测试-I2C master modul which has a avalon-MT interface that can be attached to Altera SOC system. It provides NiosII I2C communication capability . This mo
42cb47db-de04-443e-ac41-d950bce5756a
- vhdl uart代码，自己调试用的，大家指点，支持一下-vhdl uart
verilog
- verilog 的很有用的教程 特别是对初学者会有很大的启发 希望对大家有用-verilog' s very useful especially for beginners course will be a source of inspiration to all of us hope that useful
intfit
- 基于Farrow结构的平方内插器，其中输入为8位的小数插值相位和8位的输入数据，实现8位数据输出，仿真验证结果显示此种方法占用资源少。-Farrow structure based on the square interpolator, which enter the decimal for the 8-bit and 8-phase interpolation of the input data to achieve 8-bit data output, simulation results
wb_flash_latest[1].tar
- flash 控制器，用verilog描述，希望对大家有帮助-flash controller!
memory_cores_latest[1].tar
- 存储器控制器，是Verilog描述，希望对大家有帮助！-Memory controller
04_FPGA_Architecture
- oh my god. We can this book. Now 1..2..3 read it
basic-fpga-arch-xilinx
- you need book. I need book. We can share. Good luck