资源列表
fenpinqi
- 偶数倍分频：偶数倍分频应该是大家都比较熟悉的分频，通过计数器计数是完全可以实现的。如进行N倍偶数分频，那么可以通过由待分频的时钟触发计数器计数，当计数器从0计数到N/2-1时，输出时钟进行翻转，并给计数器一个复位信号，使得下一个时钟从零开始计数。以此循 环下去。这种方法可以实现任意的偶数分频。-Dual frequency many times: even several times frequency should be more familiar with all the sub-fre
xilinx_ref_guide
- Xilinx Blockset Reference Guide
AD9826
- ad9826使用说明，元件。英文的福田余iruru同意4-ad9826
Spartan-3_NeuralNetwork_3-layer_feedforward_backp
- The aim of this project is the design and implementation of a system simulating a NN in the Spartan-3 Starter Board of Xilinx. The NN will be a 3-layer feedforward backpropagation.- The aim of this project is the design and implementation of
FIR_Direkt_BAB_P
- VHDL编写的代码。采用流水线方法实现的FIR滤波器。22阶。Fa=48kHz, Fc=10KHz。可用ModeSim仿真并FPGA实现-Code written in VHDL. Line method using the FIR filter. 22 bands. Fa = 48kHz, Fc = 10KHz. Can be used to achieve ModeSim simulation and FPGA
adc_dac_normalizador_v_2
- This an examples for converting decimal number to binary-This is an examples for converting decimal number to binary
QUARTUSIIIntroduce
- 本手册针对的读者是 Quartus II 软件的初学者，它概述了可编程逻辑设计中 Quartus II 软件的功能-This manual is aimed at readers of the Quartus II software for beginners, it provides an overview of programmable logic in the Quartus II design software
cpld_config
- spartan3e starter kit,cpld 的配置文件-spartan3e starter kit,cpld configuration file
sfsdfdsf
- 基于EDA的秒表的VHDL源代码，计数时间高达24小时。-VHDL-based EDA source code of a stopwatch, counting time up to 24 hours.
bible
- 基于EDA的三八译码器，四选一优先选择器，楼梯开关电路，包含程序运行波形图。-EDA-based decoder of the 38, four elections to choose a priority, and the staircase switch circuit, including wave run.
opencores_can
- CANIP核 CAN总线以报文为单位进行数据传送,报文的优先级结合在11位标识符中,具有最低二进制数的标识符有最高的优先 级。-CANIPCore