资源列表
min_max_finder_part3_M4
- 给定一组数据，从这一组数据中找出他们的最大值和最小值-to get the maximam and minimam of a series of numbers
Verilog-testbench-and-memory-I2C
- verilog编写的测试平台，内含具体project和储存模块的编写-Verilog testbench for digital design Memory I2C module Assignment
DELAY
- 一个用元件实现的延时例程，通过这个例程可以学习元件的使用和简单的计数器延时的编程方法。-A delay routine use components to achieve through this routine can learn to use the elements and simple programming counter delay
textio03
- 在QUARTUS II 下用 MODELSIM 仿真的例子，用TEXTIO文件进行仿真，带读取数据的文本文件，注释也比较详尽。对初学仿真有帮助。-In QUARTUS II with MODELSIM simulation examples, simulation with TEXTIO file, a text file with read data, comments are more detailed. Simulation helpful for beginners.
DigitalFM
- 用VHDL编写的一个全数字FM调谐接收机的源代码和详细资料，原文是英文，已经翻译成中文。 -One using VHDL digital FM tuner receiver source code and detailed information, the original is in English, has been translated into Chinese.
key
- 用VHDL编写的一个按键检测的例子，采用了防抖，每按一下按键，输出一个按键脉冲。-Examples of VHDL prepared by the detection of a button, using the image stabilization, each key is pressed, the output pulse of a button.
fir_test01
- 在quartus ii 环境下，用VHDL语言编写的基于ALTERA 的IP核的FIR低通滤波器。 -In quartus ii environment, using VHDL language ALTERA FIR IP core based on the low-pass filter.
Cepin
- 使用FPGA编程器件，实现实时测频功能，语言简单-Frequency measurement
fec_encoder
- This module Implements the Forward Error Correction Encoder
carry-look-ahead-adder32
- This implements Carry look ahead adder in verilog
wallace_tree_multiplier
- this implements wallace tree multiplier in verilog
New-folder
- i have attached area efficient and low power carry select adder and with code