资源列表
+VHDL
- 很详细用VHDL写的自动售货机程序有详细的说明和设计要求实现功能-Very detailed written using VHDL vending machine procedure is described in detail and design requirements for the realization of function
uart_tx_rx_baudselct
- 使用verilog语言设计的一个uart的源码，可以进行波特率选择。-A uart source code using Verilog language design, baud rate selection.
p4_adder.tar
- 用vhdl实现的P4加法器，包括主要元件rca加法器，carry select adder,pg模块，并提供了一个测试文件，用modelsim测试通过-P4 adder implemented using VHDL, including the major component such as: rca adder, carry select adder, pg module,in addition provides a test file, all modules have been teste
led
- 定时器中断的例程，实现一秒定时，并在led灯上显示- Writes routine which a timer interrupts, realizes one second fixed time, and demonstrated on the led lamp
SDRAM_Verilog
- 本源码由Verilog语言编写，用硬件实现SDRAM的读写和存储数据功能，包括SDRAM的控制模块、初始化模块、读写模块等！-The source the Verilog language, implemented in hardware SDRAM read and write and store data, including SDRAM control module, initialization module, reader module, etc!
exp2_fpga
- Arithmetic logic unit
gcd_performence
- 基于流水线设计的性能优先的gcd算法的verilog 代码 频率可达500M-based pipeline design gcd for high clock
verilog
- 不同Verilog 语言间的差异，以及高版本Verilog语言的特性-Differences between different Verilog language and Verilog language version of the characteristics of high
ControllingElevatorbyFPGACode.txt
- This code is talk about how to programming FPGA to control Elevator.
PLL_50M_100M_24M
- FPGA的锁相环文件，已在DE2上实测，可用。-PLL have been measured in DE2 board, available
zhjta
- 一个五层住户电梯的设计，这个电梯必须满足一般的功能，每一层都可以对其做上楼或下楼的选择-Five households in the design of a lift, the lift must meet the general function of each layer can be upstairs or downstairs of their choice to do
11_FIR
- 11阶滤波器的verilog编程语言，可很好的实现滤波功能。-11-order filter verilog programming language, can achieve very good filtering.