资源列表
ad_rx_module
- 基于verilog的串口通信接收部分代码，欢迎下载交流！-Receiving part of the code verilog based serial communication, welcome to download the exchange!
run_module
- 基于verilog HDL的流水灯的源代码，可在FPGA开发板上运行。欢迎大家下载交流！-Based on the water lights verilog source code, welcome to download the exchange! ! !
vga_dis_module
- VGA接口通信程序，欢迎大家下载交流！使用时需要修改对应引脚~-VGA interface communication program, are welcome to download the exchange! Need to be modified when using the corresponding pin ~
PLL_1
- Phase lock loop generation for vhdl (DE2 board)
8b10b_encdec_latest.tar
- decoder of 8b8c connector
a_vhd_16550_uart_latest.tar
- uart descr iption vhdl
udp_ip_stack_latest.tar
- Udp-IP Stack for ethernet on fpga (vhdl descr iption)
Dual_ram_verilog_CODE
- 写了FIFO中要用到的双口RAM的模块,FIFO中的RAM只用于读数据,输出数据,用写时针采集信号,读时针那一端不用读时针来采样.-Written to use the FIFO dual port RAM module, FIFO in the RAM is only used to read data, output data, the clock signal acquisition with write and read without reading that end of the h
FPGA_CLK
- FPGA时钟分频的源代码，已经测试通过！-FPGA clock divider source code, has been tested!
FPGA_UART
- 在Verilog环境下，实现多个串口的功能，支持波特率，数据位，停止位可设。-In Verilog environment, to achieve multiple serial ports, support for baud rate, data bits, stop bits can be set.
shuzizhong
- 我做的是基于fpga的一个数字钟的设计用的是xilinx ise开发环境-What I do is design a digital clock based fpga xilinx ise with the development environment
MID_FILTER
- 中值滤波算法的verilog实现，可用于相关算法在基于FPGA的嵌入式图像处理系统中。-Median filtering algorithm verilog realization available FPGA-based embedded image processing system.