资源列表
Lab10_Part1
- Verilog code for Altera Part1 Lab10
water
- 基于FPGA的流水灯设计，可以检验晶振是否正常工作，时钟晶振为48M-Running water light design based on FPGA makes possible the testing of crystals is working correctly, the clock crystals of 48m
led_water
- 用VERIlog语言编写的FPGA流水灯程序，已经实现，可以立即使用-VERIlog language FPGA with light water program has been implemented, you can use immediately
tuxingandvhdlsheji
- FPGA开发实例之 图形和VHDL混合输入的电路设计。 注：编译时请将文件放在英文目录下面-The FPGA development instance of graphic and VHDL mixed input circuit design. Note: please send files in directories below in English at compile time
7renbiaojueqi
- FPGA开发实例 之 用VHDL设计七人表决器-The FPGA development instance of the design with VHDL voter of seven people
duogongnengshuzizhong
- FPGA开发实例 之 多功能数字钟.多功能数字钟应该具有的功能有：显示时－分－秒、整点报时、小时和分钟可调等基本功能。-FPGA development instance of multi-function digital clock. The function of the multi-function digital clock should have are: show- points- second, hour, hour and minute basic function such a
shuzimiaobiao
- FPGA开发实例 之 数字秒表.七段码管显示.秒表由于其计时精确，分辨率高（0.01秒），在各种竞技场所得到了广泛的应用。-FPGA development instance of digital stopwatch. 7 yards tube display. Stopwatch because its timing precision, high resolution (0.01 seconds), the income to the extensive application in var
8wei7duanshumaguanxianshi
- FPGA开发实例 之 八位七段数码管动态显示电路的设计.-The FPGA development instance of eight seven segment digital tube dynamic display circuit design.
IMAGE_ROTATION_v2
- 基于DE2-115开发板，采用控制波动开关 SW[2:0]实现图像±45°，±90°旋转及VGA显示-Implementing the rotation of image based on DE2-115 board. Used switch SW[2:0] to control the orientation of rotating image(±45°&±90°).
sdram_src
- 基于FPGA的读写控制，sdram，简单易懂，verilog代码描述-FPGA-based read and write control, sdram, easy to understand, verilog code Descr iption
big_data_encoder
- 本文介绍了一个以FPGA为主控制器的多存储芯片数据采集板卡的设计。该卡通过一个符合ATA-6规范的IDE接口,使用PIO模式将数据采集板卡与上位机互联。通过FPGA控制一片高速AD进行数据采集,采集的数据通过4片电子盘并行存储,实现高速大容量数据采集。文章侧重于介绍用FPGA控制电子盘并行读写的方法-This paper introduces an FPGA-based controller design multi memory chip data acquisition board. The
cmp42
- 用于乘法器设计，8位Booth译码乘法器，4-2压缩结构，加速乘法运算速度-Used for the design of multiplier, 8 Booth decoding multiplier, 4-2 compressed structure, accelerate the multiplication rate